1. Field of the Invention
The present invention relates to a semiconductor device with a boosting circuit sing a 2-step boosting operation.
2. Description of the Related Art
FIG. 1 is a block diagram showing the structure of a row decoder in a cell array block of a usual semiconductor memory device. A plurality of row decoders 33a to 33n are connected with a row system power supply line 31 which is connected with a row decoder power supply VPX. A plurality of word lines 34 extend from each of the row decoders 33a to 33n to a corresponding one of memory cell arrays 32a to 32n.
In a semiconductor memory such as a FLASH memory are required various criteria such as low voltage operation, low power consumption, high access speed and cost reduction through chip size reduction. Under these criteria, the power supply voltage becomes low. However, it is difficult to decrease a threshold voltage (hereinafter, to be referred to as Vtm) of a cell.
There are coupling capacitance between a word line, a floating gate and a substrate containing diffusion layers in one memory cell. A writing system by use of channel hot electrons is generally adopted in a NOR type cell array 32 in which a plurality of memory cell are connected with a same bit line. In this case, the potential of the floating gate is increased due to the drain voltage in the non-selected memory cell on the same bit line in a memory cell writing operation, so that a leak current flows. The leak current changes based on the threshold voltage Vtm of the cell, the leak quantity increases in a low threshold voltage Vtm.
Also, leak currents of the cells connected to the same bit line are added for the number of cells. Consequently, the write drain potential drops so that it becomes impossible to perform the write operation. Accordingly, the minimum of on cell threshold voltage Vtm must be suppressed to about 1 V. Also, the deviation of threshold voltages Vtm of the memory cells in case of erasure is about 1 V. In consideration of the above matters, the upper limit of the threshold voltage Vtm is 2 V. If the threshold voltage is lower than 2 V, there is the possibility that the memory cell cannot be turned on, even if a power supply potential is applied to a word line.
Also, to speed up the memory device, the on current of the memory cell must be increased. Therefore, the word potential as many as about 3.5 V is required.
Therefore, it is necessary to increase the word potential at the time of the reading operation. As the technique of increasing the word potential, there are a charge pump system in which the word potential is increased by a charge pump, and a voltage boosting system in which the word potential is increased through the voltage boosting by use of capacitance coupling.
In case of the charge pump system, the charge pump must be always operated before the reading operation so as to increase the word potential. Therefore, this method cannot achieve the low power consumption. Also, when the current is set to 0 .mu.A at a standby mode, several .mu.s is required to switch the operation mode from the standby mode to a boosting mode. Therefore, the charge pump does not meet the high-speed operation. Further, if the current is increased to realize the high-speed switching, the charge pump does not meet the low power consumption criteria.
In case of the voltage boosting method, the boosting capacitor is provided to boost the word line connected to the word line power supply line to a potential higher than a power supply potential VDD. Only when the word line potential should be increased, the potential of one electrode of the boosting capacitor is increased from the ground (GND) potential to the power supply potential VDD so that it is possible to increase the word line potential at high speed. Therefore, a voltage boosting circuit needs not to always operate at the time of access. Thus, the consumption current can be reduced at the time of access and can be set to 0 .mu.A in the standby mode. In this method, however, there is a limitation in the maximum voltage capable of being outputted to the word line.
FIG. 2 is a schematic circuit diagram showing the principle of a conventional example of the boosting circuit. FIGS. 3A to 3C are timing charts in various portions of the boosting circuit shown in FIG. 2.
Referring to FIG. 2, one of the electrodes of the boosting capacitor Cb is connected with the row decoder power supply VPX and the other electrode is connected with the power supply VA. Also, the external power supply potential VDD is connected with the row decoder power supply VPX through the switch 35. As shown in FIG. 2, in the row system power supply line 31 is a parasitic capacitor CW which is a total of a parasitic capacitance CL of the row system power supply line 31 itself and parasitic capacitances C1 to Cn of the row decoders 33a to 33n.
Supposing that the power supply potential is VDD(V), the boosting capacitor is Cb (pF), and the parasitic capacitor connected with the word line power supply potential VPX is Cw(pF), the word line potential Vword is expressed by the following equation: EQU Vword={(2.times.Cb+Cw).div.(Cb+Cw)}.times.VDD
Theoretically, the word line potential can be increased to twice of the potential of VDD if the capacitor Cb is increased to an infinite value. However, from the viewpoint of the reduction of a chip size, the boosting capacitor is desired to be as small as possible. In case of that the power supply voltage Vdd is 1.8 V, the parasitic capacitance Cw is 100 pF, and the row decoder power supply VPX potential is 3.5 V, the boosting capacitor needs to have the capacitance equal to or more than 1500 pF, in the relation between the above-mentioned potential and capacitance. When a lower voltage power supply is used, the boosting capacitor Cb needs to have a further larger capacitance. This leads the increase of chip size. Alternatively, when the power supply voltage Vdd is 1.8 V, the parasitic capacitance Cw is 100 pF, and the boosting capacitor Cb is 1500 pF, the row decoder power supply VPX potential is 3.488 V.
In conjunction with the above description, a semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-A-Showa 56-111179). In this reference, a word line is driven by a row decoder which generates a first high voltage based on a row address signal. After the first high voltage is generated, a voltage reducing unit reduces the voltage from the first high voltage to a second high voltage with a time constant. Thus, when an address signal is switched, the voltage can be reduced quickly.
Also, a boosting circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Showa 63-139426). In this reference, the boosting circuit is composed of first to third MOS transistors and a capacitor. The first MOS transistor is connected at one electrode to a power supply line. The second MOS transistor has one electrode connected to a first input terminal, the other electrode connected to a gate electrode of the first MOS transistor, and a gate electrode connected to the power supply line. The third MOS transistor has one electrode connected to the other electrode of the first MOS transistor, the other electrode connected to a ground potential, and a gate electrode connected to a second input terminal. The capacitor is connected at one electrode to a node between the gate electrode of the first MOS transistor and the other electrode of the second MOS transistor. Also, the capacitor is connected at the other electrode to a node between the other electrode of the first MOS transistor and one electrode of the third MOS transistor. A resistor is interposed between the one electrode of the first MOS transistor and the power supply line or the other electrode of the first MOS transistor and the one electrode of the third MOS transistor.
Also, a boosting circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 5-189970). In this reference, the boosting circuit is composed of boosting capacitors C1 to C4. The boosting capacitors C1 to C4 are connected substantially in parallel to be charged to a predetermined potential when a control signal S1 is in a low level. Also, the boosting capacitors C1 to C4 are connected substantially in series to be boosted when the control signal S1 is in a high level. The boosting circuit is further composed of a boosting capacitor C5 and MOSFETs Q5 and Q6. The gate voltages of MOSFET Q1 to Q4 for charging the boosting capacitors C1 to C4 based on a control signal S2 which is made effective prior to the control signal S1.
Also, a 2-stage boosting circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-139077). In this reference, the boosting circuit is composed of a low voltage power supply Vcc, a high voltage power supply Vch, a NMOS transistor QN1 and a PMOS transistor QN2. The output of the NMOS transistor QN1 driven from 0 V to (Vcc-Vth) in response to a pre-boost signal IN1. The output of the PMOS transistor QN2 driven from the (Vcc-Vth) to the high voltage Vch in response to a pre-boost signal IN2.
Also, a word line driving method is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-191093). In this reference, a word line enable signal is generated from a part of an address signal by a main row decoder. A word line boosting signal is generated from another part of the address signal by a sub row decoder. A boosting element transfers the word line enable signal to a boost node via a first power supply voltage source. A high voltage transfer means input a potential of the boost node and transfers the word line boosting signal to a word line. After the word line enable is switched from the low level to the high level, the word line boosting signal is switched from the ground potential to a high potential such that the word line is driven. Thereafter, the first power supply voltage source changes from a high potential state to a low potential state.